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// IP VLNV: xilinx.com:ip:ace5lite_traffic_gen:1.0
// IP Revision: 1

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
axi_tg_pl_master_to_ddr your_instance_name (
  .s_axi_aclk(s_axi_aclk),                      // input wire s_axi_aclk
  .s_axi_aresetn(s_axi_aresetn),                // input wire s_axi_aresetn
  .core_ext_start(core_ext_start),              // input wire core_ext_start
  .m_axi_awid(m_axi_awid),                      // output wire [0 : 0] m_axi_awid
  .m_axi_awaddr(m_axi_awaddr),                  // output wire [47 : 0] m_axi_awaddr
  .m_axi_awlen(m_axi_awlen),                    // output wire [7 : 0] m_axi_awlen
  .m_axi_awsize(m_axi_awsize),                  // output wire [2 : 0] m_axi_awsize
  .m_axi_awburst(m_axi_awburst),                // output wire [1 : 0] m_axi_awburst
  .m_axi_awlock(m_axi_awlock),                  // output wire [0 : 0] m_axi_awlock
  .m_axi_awcache(m_axi_awcache),                // output wire [3 : 0] m_axi_awcache
  .m_axi_awprot(m_axi_awprot),                  // output wire [2 : 0] m_axi_awprot
  .m_axi_awqos(m_axi_awqos),                    // output wire [3 : 0] m_axi_awqos
  .cmdram_unused(cmdram_unused),                // output wire [83 : 0] cmdram_unused
  .m_axi_awakeup(m_axi_awakeup),                // output wire m_axi_awakeup
  .m_axi_awvalidchk(m_axi_awvalidchk),          // output wire m_axi_awvalidchk
  .m_axi_awidchk(m_axi_awidchk),                // output wire [1 : 0] m_axi_awidchk
  .m_axi_awaddrchk(m_axi_awaddrchk),            // output wire [6 : 0] m_axi_awaddrchk
  .m_axi_awlenchk(m_axi_awlenchk),              // output wire m_axi_awlenchk
  .m_axi_awctlchk0(m_axi_awctlchk0),            // output wire m_axi_awctlchk0
  .m_axi_awctlchk1(m_axi_awctlchk1),            // output wire m_axi_awctlchk1
  .m_axi_awctlchk2(m_axi_awctlchk2),            // output wire m_axi_awctlchk2
  .m_axi_awuserchk(m_axi_awuserchk),            // output wire [1 : 0] m_axi_awuserchk
  .m_axi_awakeupchk(m_axi_awakeupchk),          // output wire m_axi_awakeupchk
  .m_axi_awsnoop(m_axi_awsnoop),                // output wire [3 : 0] m_axi_awsnoop
  .m_axi_awdomain(m_axi_awdomain),              // output wire [1 : 0] m_axi_awdomain
  .m_axi_awstashniden(m_axi_awstashniden),      // output wire m_axi_awstashniden
  .m_axi_awstashnidchk(m_axi_awstashnidchk),    // output wire m_axi_awstashnidchk
  .m_axi_awstashnid(m_axi_awstashnid),          // output wire [10 : 0] m_axi_awstashnid
  .m_axi_awstashlpiden(m_axi_awstashlpiden),    // output wire m_axi_awstashlpiden
  .m_axi_awstashlpidchk(m_axi_awstashlpidchk),  // output wire m_axi_awstashlpidchk
  .m_axi_awstashlpid(m_axi_awstashlpid),        // output wire [4 : 0] m_axi_awstashlpid
  .m_axi_awuser(m_axi_awuser),                  // output wire [7 : 0] m_axi_awuser
  .m_axi_awvalid(m_axi_awvalid),                // output wire m_axi_awvalid
  .m_axi_awready(m_axi_awready),                // input wire m_axi_awready
  .m_axi_wlast(m_axi_wlast),                    // output wire m_axi_wlast
  .m_axi_wlastchk(m_axi_wlastchk),              // output wire m_axi_wlastchk
  .m_axi_wdata(m_axi_wdata),                    // output wire [511 : 0] m_axi_wdata
  .m_axi_wdatachk(m_axi_wdatachk),              // output wire [3 : 0] m_axi_wdatachk
  .m_axi_wstrb(m_axi_wstrb),                    // output wire [63 : 0] m_axi_wstrb
  .m_axi_wstrbchk(m_axi_wstrbchk),              // output wire [0 : 0] m_axi_wstrbchk
  .m_axi_wvalid(m_axi_wvalid),                  // output wire m_axi_wvalid
  .m_axi_wvalidchk(m_axi_wvalidchk),            // output wire m_axi_wvalidchk
  .m_axi_wready(m_axi_wready),                  // input wire m_axi_wready
  .m_axi_bid(m_axi_bid),                        // input wire [0 : 0] m_axi_bid
  .m_axi_bresp(m_axi_bresp),                    // input wire [1 : 0] m_axi_bresp
  .m_axi_bvalid(m_axi_bvalid),                  // input wire m_axi_bvalid
  .m_axi_bready(m_axi_bready),                  // output wire m_axi_bready
  .m_axi_breadychk(m_axi_breadychk),            // output wire m_axi_breadychk
  .m_axi_arid(m_axi_arid),                      // output wire [0 : 0] m_axi_arid
  .m_axi_araddr(m_axi_araddr),                  // output wire [47 : 0] m_axi_araddr
  .m_axi_arlen(m_axi_arlen),                    // output wire [7 : 0] m_axi_arlen
  .m_axi_arsize(m_axi_arsize),                  // output wire [2 : 0] m_axi_arsize
  .m_axi_arburst(m_axi_arburst),                // output wire [1 : 0] m_axi_arburst
  .m_axi_arlock(m_axi_arlock),                  // output wire [0 : 0] m_axi_arlock
  .m_axi_arcache(m_axi_arcache),                // output wire [3 : 0] m_axi_arcache
  .m_axi_arprot(m_axi_arprot),                  // output wire [2 : 0] m_axi_arprot
  .m_axi_arqos(m_axi_arqos),                    // output wire [3 : 0] m_axi_arqos
  .m_axi_arvalidchk(m_axi_arvalidchk),          // output wire m_axi_arvalidchk
  .m_axi_aridchk(m_axi_aridchk),                // output wire [1 : 0] m_axi_aridchk
  .m_axi_araddrchk(m_axi_araddrchk),            // output wire [6 : 0] m_axi_araddrchk
  .m_axi_arlenchk(m_axi_arlenchk),              // output wire m_axi_arlenchk
  .m_axi_arctlchk0(m_axi_arctlchk0),            // output wire m_axi_arctlchk0
  .m_axi_arctlchk1(m_axi_arctlchk1),            // output wire m_axi_arctlchk1
  .m_axi_arctlchk2(m_axi_arctlchk2),            // output wire m_axi_arctlchk2
  .m_axi_aruserchk(m_axi_aruserchk),            // output wire [1 : 0] m_axi_aruserchk
  .m_axi_arsnoop(m_axi_arsnoop),                // output wire [3 : 0] m_axi_arsnoop
  .m_axi_ardomain(m_axi_ardomain),              // output wire [1 : 0] m_axi_ardomain
  .m_axi_aruser(m_axi_aruser),                  // output wire [7 : 0] m_axi_aruser
  .m_axi_arvalid(m_axi_arvalid),                // output wire m_axi_arvalid
  .m_axi_arready(m_axi_arready),                // input wire m_axi_arready
  .m_axi_rid(m_axi_rid),                        // input wire [0 : 0] m_axi_rid
  .m_axi_rlast(m_axi_rlast),                    // input wire m_axi_rlast
  .m_axi_rdata(m_axi_rdata),                    // input wire [511 : 0] m_axi_rdata
  .m_axi_rresp(m_axi_rresp),                    // input wire [1 : 0] m_axi_rresp
  .m_axi_rvalid(m_axi_rvalid),                  // input wire m_axi_rvalid
  .m_axi_rready(m_axi_rready),                  // output wire m_axi_rready
  .m_axi_rreadychk(m_axi_rreadychk),            // output wire m_axi_rreadychk
  .irq_out(irq_out)                            // output wire irq_out
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file axi_tg_pl_master_to_ddr.v when simulating
// the core, axi_tg_pl_master_to_ddr. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

